en.Wedoany.com Reported - Listen AI plans to release its Nebula series of edge-side large model AI inference chips by the end of this year, targeting the underlying computing power demand behind the explosion of terminal intelligent hardware. The series is natively designed for Transformer-based large models, expected to achieve a 10x computing acceleration and support for 10x model parameter scale, with inference speeds exceeding 100 tokens/s. It also adopts 3D-DRAM stacking technology to increase memory bandwidth to 5-10 times that of traditional LPDDR.
At the recently concluded 2026 World Artificial Intelligence Conference (WAIC 2026), the focus of the AI sector has shifted from cloud supercomputing clusters to pan-terminal hardware such as smartphones, AI PCs, humanoid robots, intelligent cockpits, and whole-home controllers. This trend imposes new requirements on underlying computing chips: they must achieve efficient, stable, and scalable local inference of large models under the constraints of low power consumption, miniaturization, and low cost.
The development of edge-side large models has moved from verifying feasibility ("can it run?") to the practical implementation phase of "real-time, stable, low-power" usability. Scenarios like robotics and intelligent cockpits require millisecond-level critical decision responses and cannot rely on cloud networks long-term. The logic of chip competition has shifted from sheer TOPS peak computing power to full-dimensional system efficiency, with comprehensive metrics such as actual tokens/s processing speed, first-token latency, operating power consumption, memory bandwidth, and software toolchain becoming key.
Addressing computing power utilization, the Nebula chip inversely defines the computing architecture based on the algorithmic characteristics of large models, adapting to the dynamic loads of the Prefill and Decode stages. In terms of memory bandwidth, 3D-DRAM stacking shortens the data path between storage and computation. The series also supports pairing with different capacities of stacked memory to suit various model specifications, and enables elastic scaling of computing power through chip cascading. The accompanying toolchain, SDK, and reference designs aim to lower the barrier for edge-side large models to move from prototypes to mass production.
Han Chaoyang, Vice President of Marketing at Listen AI, noted during WAIC 2026 that edge-side AI chips natively designed for large model inference algorithms remain scarce on the market.
Listen AI's cumulative chip shipments have exceeded the billion-unit level. In the voice direction, its solutions have entered the supply chains of white goods leaders such as Haier and Midea; in the vision direction, it brings local AI capabilities to devices like scanning pens, handheld gimbals, and smart locks. The Nebula series extends from original perception capabilities to understanding, generation, and reasoning. Han Chaoyang believes that in the future, edge-side small-model perception chips will handle low-power real-time perception, while cognitive large-model chips will undertake complex semantic understanding, with both working synergistically to upgrade the edge-side AI experience.
In terms of application industrialization, Listen AI has initiated joint pre-research with companies including Lenovo, Lingdong Robot, Haier, Midea, and Mianbi, advancing the deployment of edge-side large model AI inference chips in real terminal scenarios across four major directions: AI PCs, robotics, smart homes, and intelligent cockpits.
