Recently, Huawei officially unveiled "Tao's Law (τ)," proposing "time-based scaling" as a replacement for "geometric scaling" as the guiding principle for semiconductor evolution. As a systematic summary of six years of breakthrough practices, this proposition quickly garnered intense attention.

The physical boundary "wall" of Moore's Law is clearly visible, and path selection is a proposition facing the entire semiconductor industry. Having confronted this "wall" earlier, Huawei's solution is "Tao's Law."

As the first new principle for semiconductor evolution proposed by a Chinese enterprise, "Tao's Law" starts anew, pursuing collaborative optimization across four layers: devices, circuits, chips, and systems. Over the past six years, Huawei has designed and mass-produced 381 chips based on this paradigm, laying a solid empirical foundation.

Therefore, for the domestic semiconductor industry, which has long been in a "catch-up narrative," this proposition holds special significance—shifting from "you set the rules, I'll catch up," chasing advanced nodes and international giants, to "I propose the path, inviting the world to verify."

In a media interview, He Tingbo, Board Director of Huawei and President of the Semiconductor Business Unit, stated: "Some may join our ranks in three days, others might wait three to five years. We welcome all. More practice is needed to prove it, and we hope everyone can work together to make this endeavor better."

This is a declaration of confidence, and more so, an open invitation to the industry. With this, the true industry marathon has begun.

The reason Moore's Law was enshrined as a golden rule is not because of Gordon Moore's brilliant exposition back then, but because over the following decades, the entire semiconductor industry chain—from lithography machine companies, material suppliers, EDA (Electronic Design Automation) tool providers, design houses to foundries—continuously invested and iterated together following this law, elevating it from an empirical observation to an industry contract.

Now, a Chinese company, based on long-term practice, proposes a new methodology, striving to carve out a new industrial path of independent innovation. This new path goes beyond single-point technological breakthroughs; it requires forming a closed loop across multiple layers of technology, including architectural design capabilities, software-hardware co-optimization efficiency, advanced packaging technologies, etc.

The direction is clear. To turn this breakout path into a broad avenue, ecosystem co-construction and steadfast investment from the industry chain are needed.

For instance, the EDA tools that chip design relies on must evolve accordingly. Chip design under the guidance of "Tao's Law" is no longer optimization on a two-dimensional plane, but the stacking of three-dimensional structures, akin to shifting from "building bungalows" to "erecting skyscrapers." However, existing mainstream EDA tools have largely evolved around planar design logic. Adapting to the new three-dimensional construction method requires upgrading the underlying tools, such as redesigning place-and-route methods and improving verification approaches, which is equivalent to rewriting the entire toolchain.

Based on "Tao's Law," Huawei has already accumulated full-stack technical tools like logic folding and chiplet packaging. In the future, these need to be shared with the industry in an open and reusable manner, enabling different manufacturers to "speak the same language," thereby better achieving synergy and accelerating the ecosystem construction process.

It is conceivable that this will be a "lane-changing marathon" testing resolve and endurance. How long this road is and where it will ultimately lead needs to be answered jointly by the semiconductor industry.