The complex sulci and gyri folds on the surface of the cerebral cortex, which previously required expensive large-scale computing equipment for lengthy offline computation to reconstruct in real-time on a computer, have now been revolutionized by a thumb-sized chip.
A team led by Yang Yuchao, a New Cornerstone Investigator and professor at the School of Integrated Circuits, Peking University, in collaboration with the team led by researcher Song Zhitang from the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, has successfully developed the world's first neurodynamic system chip based on phase-change memristors. For the first time, the single-step latency of such complex computations has been compressed to 2.12 milliseconds, achieving a speedup of 50 to 478 times compared to current advanced graphics processing units (GPUs) in tasks such as cerebral cortex reconstruction, breaking through the real-time computing bottleneck that has plagued neurodynamics for half a century. The related findings were published in Science early on the 3rd.
Yang Yuchao told reporters that to enable machines to model and understand the physical world in real-time like the human brain, a "neurodynamic system" that combines neural networks with differential equations is needed. It can reconstruct smooth and accurate three-dimensional brain structures from incomplete, noisy data, holding immense application potential.
However, traditional computing architectures face a core bottleneck: the separation of storage and computation. During the solving process, massive intermediate variables shuttle back and forth between memory and processor, akin to a vast data factory where much time is wasted on transportation, resulting not only in significant latency but also high power consumption.
Faced with this challenge, the research team found a breakthrough solution in the physical properties of the memristor itself. They utilized the unique "conductance drift" phenomenon of phase-change memory—where within a certain time window, the conductance change is predictable and precisely controllable.
Based on this, the team proposed a new paradigm of "controllable in-memory computing," directly encoding the most time-consuming adaptive step-size search in dynamic system solving into the physical conductance evolution process of the device, completing the computation in situ within the memory cell. In simple terms, operations that previously required complex digital circuits to repeatedly execute, such as calculations, cache access, and data movement, are now handled by the physical laws of the device itself.
More notably, the team also mapped neural network weights onto the multi-level conductance states of the phase-change memory, synchronously completing matrix multiplication and addition operations within the same array. Thus, the two core computational tasks were unified and integrated into a compute-in-memory array with a total area of only 0.28 square millimeters. This chip, fabricated using a 40-nanometer process, operates at a frequency of 50 megahertz, requires only a 9-stage pipeline for single-step integration, and ultimately achieves a single iteration latency of 2.12 milliseconds, pushing neurodynamic hardware into the millisecond era for the first time.
"The performance is exhilarating," said Yang Yuchao. Under equivalent computations, this chip achieves a speedup of 3.82 to 36.27 times and reduces power consumption by 11.75 to 24.73 times compared to current state-of-the-art dedicated accelerators. In high-fidelity reconstruction tasks of the cerebral cortex surface, it even achieves a speedup of up to 478.18 times compared to the NVIDIA A100 GPU. The reconstructed cortical mesh is smooth and topologically consistent, accurately depicting complex folded structures while effectively suppressing artifacts and self-intersection defects common in traditional methods.
Yang Yuchao stated that this breakthrough opens up entirely new possibilities for brain-computer interfaces and the diagnosis and treatment of brain diseases. In the future, personalized, dynamic digital twins of the brain could become a reality, providing a real-time hardware foundation for intraoperative neural navigation, early screening for Alzheimer's disease, and personalized interventions.
What is "Controllable In-Memory Computing"?
If a traditional computer is compared to an office, the processor is the "calculator" sitting in the center, and the memory is the "filing cabinets" lining the walls. For every calculation, the calculator must get up to fetch data, compute, and then return—time is wasted on the journey. This is the famous "von Neumann bottleneck": the separation of storage and computation, where data movement cripples efficiency.
The "in-memory computing" approach is straightforward: let the filing cabinets learn to do the accounting themselves. Data no longer needs to be moved back and forth; instead, computation is completed in situ within the memory cells. This sounds perfect, but implementing it is fraught with difficulties—memory cells are inherently designed only to "remember." Making them "compute" simultaneously, and do so accurately and stably, is already a challenge.
The greater difficulty lies in "controllability." Computation is not like simple addition or subtraction; many tasks require dynamic adjustment and adaptive decision-making. How to endow a set of physical devices with the ability to "respond on the fly" is a key threshold for in-memory computing to become a reality.
The breakthrough came from a "counter-intuitive" idea: utilizing the characteristic of device conductance drifting in a predictable pattern—a property once considered a "defect." If its trajectory of change can be understood, this drift can be tamed into computational capability—no longer requiring digital circuits to repeatedly read, write, and compare, but allowing the physical process itself to complete the computation.
This is the core idea of "controllable in-memory computing": enabling memory cells to "compute" while "remembering," in a manner set by the designer and within a controllable range. Storage is computation, and the entire process is precisely controllable. Chips developed based on this paradigm can compress complex computations to the millisecond level, improving energy efficiency by tens or even hundreds of times.