en.Wedoany.com Reported - US-based Intel has established advanced packaging as a core pillar of its foundry strategy, with its Embedded Multi-die Interconnect Bridge (EMIB) technology designed to help AI accelerators, network chips, and high-performance computing processors overcome the physical scaling limits of traditional monolithic chips. Mark Gardner, Vice President and General Manager of Intel Foundry Packaging and Test Business Group, introduced in a technical blog that the EMIB-T architecture is focused on addressing growing package sizes while improving manufacturing efficiency.
As AI processors increasingly rely on multiple compute chips and large-capacity high-bandwidth memory (HBM) stacks, traditional 2.5D packaging methods based on full silicon interposers are facing mounting economic and manufacturing challenges. Intel noted that large interposers consume significant silicon area, and larger package sizes lead to lower wafer utilization. EMIB-T uses small embedded silicon bridges only where high-bandwidth chip-to-chip connections are needed. The architecture employs Through-Silicon Vias (TSV) to improve power delivery and uses an organic substrate as the main package structure. Intel stated that this bridging approach achieves approximately 90% wafer utilization, compared to the lower utilization in large interposer designs. The company also mentioned support for open chip interconnect standards, including Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW).
Intel has outlined an aggressive scaling roadmap for future multi-chip systems. Current EMIB implementations can support package sizes exceeding eight times the standard reticle size, corresponding to approximately 6,800 square millimeters. Intel expects to support packages exceeding twelve times the reticle size by 2028, approaching 10,000 square millimeters. The company stated that this configuration can integrate 16 or more HBM4 or HBM5 memory stacks, interconnected via over 30 EMIB-T bridges. Intel plans to combine EMIB-T with its Foveros 3D stacking technology to create an architecture known as "EMIB 3.5D," meeting the increasingly complex design requirements of AI infrastructure.
"By combining EMIB-T with Foveros 3D stacking, Intel Foundry is building a modular advanced packaging platform capable of supporting next-generation AI and high-performance computing systems," said Mark Gardner, Vice President and General Manager of Intel Foundry Packaging and Test Business Group.
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