en.Wedoany.com Reported - IBM (USA) announced on June 25 (local time) what it claims to be the world's first sub-1nm chip technology. The transistor architecture corresponds to the 0.7nm (7 angstrom) node, demonstrating further improvements in circuit integration density as miniaturization approaches physical limits.
The new chip integrates approximately 100 billion transistors on an area the size of a fingernail, roughly twice the density of the 2nm chip released by the company in 2021. Public technical data shows that compared to the 2nm node, performance can improve by up to 50%, or power efficiency by 70%, potentially enhancing processing capabilities for generative AI, cloud infrastructure, and next-generation electronic devices. IBM explains that this also helps extend battery life and accelerate AI model training and inference.
The core technology lies in the newly developed three-dimensional transistor structure called "nanostack." This is an industry-first nanosheet-based three-dimensional design achieved by vertically stacking and interleaving transistors. Unlike previous planar miniaturization approaches, the nanostack utilizes the vertical Z-axis, which IBM describes as "like a city growing upward to accommodate more content within the same footprint."
This technology significantly contributes to generative AI. By improving integration density and power efficiency, it can accelerate AI model training and inference. Additionally, research presented at "VLSI 2026" indicates that the nanostack structure can shrink on-chip SRAM by 40%. IBM explains that this meets the high-bandwidth data demands required for advanced AI workloads, aiming to support the increasing data processing loads accompanying the scaling of generative AI in terms of density, energy efficiency, and memory bandwidth.
IBM states that this is the first time logic technology has fallen below the 1nm node, marking the entry into the "angstrom era" where dimensions approach just a few atoms. The company's semiconductor roadmap anticipates that with the nanostack structure, miniaturization will continue for at least the next decade.
Development work is being conducted at the research facility in Albany, New York, USA, which will later introduce ASML's "High NA EUV" lithography equipment. IBM is advancing manufacturing processes and tool development in collaboration with partners including Japan's Tokyo Electron, SCREEN Semiconductor Solutions, and the US-based Lam Research. IBM indicates that mass production of the nanostack technology for sub-1nm nodes could potentially begin within the next five years.
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