China's Memory Giant CXMT Achieves Major Breakthrough in DRAM Materials!

en.Wedoany.com Reported - ChangXin Memory Technologies (CXMT), China's memory giant and a latecomer in the DRAM industry, is rapidly narrowing the technology gap with industry leaders.

According to reports, the company has successfully applied high-dielectric-constant (High-k) dielectric materials, previously dominated by leading memory manufacturers, to its latest-generation DRAM products, which have now entered mass production.

In response, Samsung Electronics and SK Hynix are accelerating the development of next-generation architectures such as 4F² and 3D DRAM to maintain their technological leadership.

Jeongdong Choi, Senior Vice President at TechInsights, presented the latest development roadmap for advanced DRAM technology during a memory industry trend webinar on the 27th.

Full Adoption of Advanced High-k Materials to Rapidly Catch Up with Industry Leaders

The global DRAM market has long been dominated by the "Big Three": Samsung Electronics and SK Hynix of South Korea, and Micron of the United States. These three companies are continuously expanding shipments of high-value AI memory products through the commercialization of 12nm-class DRAM and High Bandwidth Memory (HBM).

However, Chinese memory manufacturers are catching up quickly. CXMT, currently the largest DRAM player in China, has already commercialized DDR5 and LPDDR5 products based on G4, a 16nm-class process.

Recently, CXMT has further begun adopting advanced materials in DRAM transistors that were previously used primarily by top-tier memory manufacturers.

"Importantly, our analysis shows that CXMT has successfully introduced High-K Metal Gate (HKMG) technology into its G4 process as well as LPDDR5X products," Choi said.

High-k materials are used in insulating layers to reduce leakage current between circuits. Because they can store more charge at the same voltage, they enable more aggressive device scaling compared to traditional silicon dioxide (SiO₂) gate dielectrics.

Samsung Electronics, SK Hynix, and Micron began adopting such materials approximately four to five years ago.

Meanwhile, CXMT is also advancing its HBM technology. According to reports, the company is currently conducting risk production of HBM2E, a third-generation HBM product, using the G3 process, an 18nm-class DRAM technology. Additionally, the company is sampling HBM3 based on the G4 process.

"CXMT still needs to catch up with leading manufacturers by two generations, but its HBM roadmap continues to progress toward higher-performance memory solutions," Choi said. "Its G5 process, a 15nm-class DRAM technology, is also under development."

DRAM Big Three Shift Toward 4F² and 3D DRAM

Samsung Electronics, SK Hynix, and Micron are striving to maintain their technological edge by developing next-generation DRAM below 10nm, known as the D0a node. Among these, 4F² and 3D DRAM, which can fundamentally change the traditional DRAM cell structure, are emerging as the most likely next-generation technology paths.

"Based on our current assessment, Samsung Electronics and SK Hynix are more likely to adopt 4F² DRAM," Choi said. "Micron, on the other hand, is more likely to transition directly to 3D DRAM."

4F² DRAM is a next-generation architecture that changes the arrangement of memory cells—the smallest units in DRAM used to store data—by transforming the traditional planar structure into a vertical one.

Here, "F²" represents the area occupied by a memory cell relative to the minimum feature size F of the manufacturing process.

Traditional DRAM typically employs a 6F² cell architecture. Reducing the memory cell area increases the storage density per unit area of DRAM, thereby improving data processing capabilities and power consumption. This is why the industry is placing increasing emphasis on the 4F² structure.

On the other hand, 3D DRAM vertically stacks memory cells that were previously arranged horizontally, achieving a three-dimensional structure by erecting bitlines or wordlines.

Bitlines and wordlines are interconnect structures used to control and operate the transistors of each memory cell.

With the 3D DRAM architecture, more memory cells can be integrated within the same chip area while also widening the spacing between transistors, which helps reduce interference between devices.

However, compared to 4F², 3D DRAM presents significantly higher technical challenges, as it requires the introduction of new materials, bonding technologies, and other complex process innovations.

"3D DRAM remains an extremely challenging technology. If commercialized at the D0a node, it would entail very high process complexity and could face yield issues," Choi said.

"Therefore, from the current perspective, 4F² DRAM is emerging as a more realistic candidate for the D0a node."