en.Wedoany.com Reported - The team led by Yang Yuchao, in collaboration with Song Zhitang's group from the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, has successfully developed the world's first neural dynamics system chip based on phase-change memristors. For the first time, the single-step latency of such complex computations has been compressed to 2.12 milliseconds, achieving a speedup of 50 to 478 times over current advanced graphics processing units (GPUs) in tasks such as cerebral cortex reconstruction. The findings were published in Science early on the 3rd.

Yang Yuchao, a New Cornerstone Investigator and professor at the School of Integrated Circuits, Peking University, explained that for machines to model and understand the physical world in real time like the human brain, a "neural dynamics system" combining neural networks with differential equations is required. Such a system can reconstruct smooth and accurate three-dimensional brain structures from incomplete and noisy data, offering immense application potential. However, traditional computing architectures suffer from the bottleneck of separated storage and computation, where massive intermediate variables are repeatedly shuttled between memory and processors during the solving process, leading to significant latency and high power consumption.

The research team found a solution in the physical properties of memristors. They leveraged the unique "conductance drift" phenomenon of phase-change memory, where conductance changes within a certain time window are predictable and precisely controllable. Based on this, the team proposed a new paradigm of "controllable in-memory computing," directly encoding the most time-consuming adaptive step-size search in dynamic system solving into the physical conductance evolution process of the device, completing the computation within the memory cell. Additionally, the team mapped neural network weights to multi-level conductance states of the phase-change memory, synchronously performing matrix multiply-accumulate operations within the same array. The two core computational tasks were integrated into a unified computing-in-memory array with a total area of only 0.28 square millimeters. This chip, fabricated using a 40-nanometer process, operates at a frequency of 50 megahertz, requires only a 9-stage pipeline for single-step integration, and ultimately achieves a single-iteration latency of 2.12 milliseconds, marking the first time neural dynamics hardware has entered the millisecond era.

Yang Yuchao stated that under equivalent computations, this chip achieves a speedup of 3.82 to 36.27 times and a power reduction of 11.75 to 24.73 times compared to the most advanced current dedicated accelerators. In the task of high-fidelity cerebral cortex surface reconstruction, it achieves a speedup of 50.38 to 478.18 times over the NVIDIA A100 GPU. The reconstructed cortical mesh is smooth and topologically consistent, accurately depicting complex folded structures while effectively suppressing artifacts and self-intersection defects common in traditional methods. This breakthrough opens new possibilities for brain-computer interfaces and the diagnosis and treatment of brain diseases. In the future, personalized and dynamic digital brain twins, as well as intraoperative neural navigation, early screening for Alzheimer's disease, and personalized interventions, will gain a hardware foundation capable of real-time operation.