en.Wedoany.com Reported - TIER IV, a Japanese open-source autonomous driving software company, has joined the "Next-Generation Edge AI Semiconductor R&D Initiative" led by the Japan Science and Technology Agency (JST) to advance the development of software-defined system-on-chips (SoCs) for Level 4 autonomous driving. Under this initiative, a research team led by Professor Yoshihiro Kawahara of the Graduate School of Engineering, The University of Tokyo, will advance research on physical AI chip design oriented toward use-case-driven and functionally differentiated approaches. TIER IV will be responsible for developing the logic design of an AI chip that efficiently processes inference for end-to-end (E2E) autonomous driving AI, with the relevant design assets and toolchains planned to be released as open source.

High-performance computing technologies, including graphics processing units (GPUs), have played a central role in driving the rapid evolution of AI. However, Level 4 autonomous driving requires AI models to operate continuously under real-world and real-time constraints, which demands new design methodologies beyond existing high-performance computing technologies to address power efficiency as well as adaptability, transparency, and verifiability.

TIER IV will independently design an AI chip that supports Autoware, the open-source autonomous driving software, and evaluate its effectiveness as a component of an SoC. In addition to the chip logic design, the compiler and related toolchains will also be open-sourced, with the aim of establishing an open ecosystem that enables semiconductor manufacturers to leverage its platform technology to accelerate the commercialization of Level 4 autonomous driving SoCs.

Autonomous driving AI increasingly relies on large-scale Transformer models to process sensor inputs such as camera images and point cloud data in an integrated manner, covering everything from perception to motion planning. This initiative will focus on Transformer inference and develop a dedicated architecture that simplifies the complex control mechanisms required for general-purpose computing. The data needed for AI model execution will be efficiently prefetched and reused within the chip to reduce power consumption associated with external memory transfers and computational control. The architecture will also integrate dedicated computational circuits for operations commonly used in Transformers, including matrix multiplication and attention mechanisms. TIER IV states that the optimization target is not only the chip's peak performance but also the performance-per-watt of the entire autonomous driving system, including Autoware. The design must support flexible deployment across different application scenarios, from embedded devices consuming a few watts to in-vehicle electronic control units consuming tens of watts.

To address the architectural adaptation challenges posed by the rapid evolution of autonomous driving AI technologies, TIER IV will introduce the Tensor Operator Set Architecture (TOSA) as a standardized intermediate representation between AI models and AI chips. Operations from AI models developed in frameworks such as PyTorch will be converted into a common TOSA representation, then optimized and code-generated for execution on the AI chip, thereby achieving loose coupling between AI frameworks and hardware. Changes in model architecture or computational methods can thus be accommodated primarily through software component updates such as compilers and runtimes, without requiring a full chip redesign. This represents a software-defined SoC design approach that enables continuous performance and power efficiency optimization through software.

In safety-critical applications such as Level 4 autonomous driving, it is necessary not only to understand the AI model itself but also to understand the internal architecture and processing flow of the computing system on which it runs. TIER IV will open-source the logic design, compiler, and related toolchains of the autonomous driving AI chip, enabling semiconductor manufacturers and developers to inspect the chip's internal architecture and software behavior, and to modify, extend, and reuse them according to their respective vehicle platforms, AI models, performance requirements, and power constraints. This approach extends Autoware's open-source philosophy from the software layer to chip design and related toolchains, with the goal of establishing a collaborative ecosystem that does not depend on specific semiconductor products or closed development environments.

The process of executing AI models on a chip involves a series of transformations, including model format conversion, computational optimization, quantization, and rounding. While these transformations improve performance and power efficiency, they can also introduce numerical differences that affect the final computational results. Based on TOSA and its operator specifications, TIER IV will build the compilation and transformation process and introduce formal verification techniques to mathematically verify, for selected transformations and operations, the numerical consistency before and after transformation and compliance with predefined error tolerances. This approach enables the transformations that AI models undergo before chip execution to be traceable and the correctness of the processing to be verifiable, providing a more reliable execution environment for autonomous driving AI.

Shinpei Kato, Founder and CEO of TIER IV, stated that AI progress has been driven by powerful computing platforms, including GPUs, and that as Level 4 autonomous driving advances toward broader deployment, these platforms need to be complemented by computing architectures designed for real-world and real-time requirements. He believes that in safety-critical environments, the ability to understand how AI models are transformed for execution and to verify processing correctness will become increasingly important; extending the open-source philosophy from software to AI chip design and related toolchains allows automakers, semiconductor manufacturers, and developers to build upon this foundation to advance their own systems, establishing a scalable, adaptable, and reliable computing foundation for Level 4 autonomous driving.

Professor Yoshihiro Kawahara noted that GPU power consumption has long been a major bottleneck in deploying battery-powered devices in physical AI applications such as robotics and autonomous driving. This project aims to overcome this constraint through functionally differentiated chip design that reverse-maps from specific use cases. He looks forward to TIER IV developing the chip responsible for high-level decision-making—the high-level behavioral layer that processes the thinking required for end-to-end physical AI and autonomous driving. As a driving force behind the Autoware open-source software, TIER IV is democratizing design from application requirements to hardware, enabling application researchers to shape semiconductors suited to their own needs. Supported by an open ecosystem, this initiative can lay the foundation for Japanese startups to continuously create high-value semiconductors.

TIER IV is an autonomous driving company focused on deep technology innovation, centered on the open-source software Autoware, providing a full suite of platforms and services from software development and vehicle procurement to operational support, and working with global partners through the Autoware ecosystem to advance the application of open-source software in the intelligent vehicle sector.