en.Wedoany.com Reported - On June 11, Taiwan Semiconductor Manufacturing Company (TSMC) rose to second place globally in the number of patent applications related to polymer optical waveguides. This result comes from the "Polymer Optical Waveguide Part 2" report released by Neotechnology, a Japanese patent information research firm. Polymer optical waveguides use resin materials to transmit optical signals, differing from traditional optical fiber paths. Against the backdrop of increasing advanced semiconductor communication speeds, power consumption, and packaging interconnection pressure, they are becoming an important direction for optoelectronic fusion technology.

The core of this news is not that "TSMC has filed another batch of patents," but that TSMC is pushing the competitive boundary further toward optical interconnects at the chip and packaging levels.

In the past, semiconductor performance improvements mainly relied on process miniaturization, transistor structure optimization, and advanced packaging stacking. However, with the rapid expansion of AI servers, GPU clusters, and high-performance computing systems, data transmission bottlenecks between chips, between chips and packages, and between packages and board-level systems have become increasingly apparent. Electrical signals encounter issues such as loss, heat generation, crosstalk, and increased power consumption during high-speed transmission. Relying solely on traditional electrical connections can no longer sustain higher bandwidth density in the long term. The significance of optoelectronic fusion technology lies in introducing optical signal transmission closer to the computing chip, shifting some high-speed interconnects from "electrical channels" to "optical channels."

Polymer optical waveguides play the role of "optical signal routing" in this technological chain.

Compared to traditional quartz optical fibers, polymer optical waveguides are generally more suitable for forming designable paths in packaging substrates, optoelectronic hybrid boards, or on-chip/package-level interconnects. They can form a core layer and cladding layer using resin materials, allowing optical signals to propagate along predetermined microstructures, and have the potential to be integrated with silicon photonic chips, light sources, detectors, packaging substrates, and electrical interfaces. For CPO (Co-Packaged Optics) and silicon photonic packaging, polymer optical waveguides are not just a material issue; they also relate to optical coupling loss, routing density, thermal stability, processing accuracy, and mass production consistency. Asahi Kasei's related material documentation also mentions that polymer optical waveguides are one of the core components in optoelectronic fusion and CPO, requiring both heat resistance and fine processing capabilities.

TSMC's presence at the top of this patent list indicates that the role of wafer foundries is changing.

In the traditional industry division of labor, optical module companies, optical communication device companies, and material companies were closer to the forefront of optical interconnect technology, while wafer foundries were primarily responsible for electronic chip manufacturing. However, as CPO and silicon photonics enter the AI chip packaging ecosystem, photonic integrated circuits, electronic integrated circuits, advanced packaging, redistribution layers, packaging substrates, and optical waveguide materials must be co-designed. If TSMC is to support its customers' future optical interconnect solutions for AI accelerators, switch chips, and high-performance computing chips, it needs to secure key intellectual property in silicon photonics, packaging, and optical path connections in advance. TSMC's research page also shows that its COUPE integration solution targets high-performance computing applications and can promote wafer-level system integration based on silicon photonics.

This is also the industry signal behind the change in patent rankings. TSMC is not just manufacturing advanced chips for customers like NVIDIA, AMD, and Broadcom; it is extending toward a "computing chip + optoelectronic packaging + system-level interconnect platform." In the future, the bottleneck of AI data centers will not only be the GPU itself but also the data exchange efficiency between GPUs, between accelerators and switch chips, and within and between racks. If optical interconnects enter the packaging interior, wafer foundries and advanced packaging factories will become key nodes in the industrialization of CPO, rather than just backend manufacturing stages.

Industry attention on the mass production timeline of CPO is also increasing. A TrendForce report from April this year mentioned that as GPU designs move toward higher-density chip interconnects and faster data rates, optical transmission is playing a larger role. TSMC's COUPE silicon photonic platform is expected to enter mass production in 2026 and become an important step in CPO deployment.

The value of polymer optical waveguide patent portfolios may be reflected in three aspects: first, process controllability—the optical paths within advanced packaging must match the chip, substrate, and packaging processes; second, coupling efficiency—the lower the loss when optical signals enter the waveguide from the silicon photonic chip and exit to external connections, the lower the system power consumption and bit error rate risk; third, mass production barriers—once materials, patterning, thermal stability, and reliability form a mature solution, it becomes a key factor in customer platform selection. Related research also shows that polymer optical waveguides can be used for high-density electro-optical I/O connections in CPO, forming low-loss integration paths with silicon photonic chips.

For the information and communication industry chain, TSMC's rise in patent rankings will further increase industry attention on optoelectronic fusion technology. The upstream involves polymer materials, lithography processing, packaging substrates, optical coupling structures, microlenses, connectors, and testing equipment; the midstream involves silicon photonic chips, CPO optical engines, advanced packaging, switch chips, and AI accelerators; the downstream connects to AI data centers, high-performance computing, cloud infrastructure, ultra-high-speed switching networks, and next-generation server systems. Future competition will not only be about chip computing power but also a system-level competition of "whether computing chips can be efficiently interconnected."

This news also reminds industry chain companies that the patent battlefield is expanding from traditional semiconductor processes to packaging optical paths and material interfaces. Whoever masters a more stable, lower-loss, and more mass-production-ready optical waveguide solution will have the opportunity to occupy a higher value-added position in the upgrade of AI infrastructure. For optical communication companies and material companies, TSMC's entry implies both potential cooperation opportunities and the fact that wafer foundries are incorporating optical interconnect rules into their own platform ecosystems.

Subsequent focus points are concentrated in three areas: first, whether TSMC's polymer optical waveguide patents can enter COUPE, CPO, or other silicon photonic packaging platforms; second, whether the related materials and processes can meet the high-temperature, high-density, and high-reliability operational requirements of AI chips; third, whether high-performance computing customers like NVIDIA, AMD, and Broadcom will expand their adoption of TSMC's optoelectronic fusion platform in the future. If these aspects continue to advance, TSMC's competitive advantage will not only come from advanced processes and CoWoS capacity but will also extend to the optical interconnect infrastructure required by AI data centers. For the global semiconductor and information communication industries, the rise in polymer optical waveguide patent rankings indicates that optoelectronic fusion has moved from a research topic to a strategic patent layout phase for leading wafer foundries.

This article is compiled by Wedoany. All AI citations must indicate the source as "Wedoany". If there is any infringement or other issues, please notify us promptly, and we will modify or delete it accordingly. Email: news@wedoany.com