en.Wedoany.com Reported - Samsung Electronics won the Best Paper award at the VLSI 2026 Symposium for its vertical stacked transistor technology, achieving the industry's smallest gate pitch for vertically stacked transistors.

Transistors are devices that amplify or control electrical signals and are considered key to determining semiconductor performance. Traditional processes have continuously increased the number of current channels from one to three, and then from three to four, to drive technological advancements.

This technology significantly alters the transistor structure by vertically stacking transistors that were originally arranged in a planar layout. Such a structure has previously been introduced in memory semiconductors, such as V-NAND for NAND flash and High Bandwidth Memory (HBM) for DRAM, overcoming area limitations through stacking, and is now expected to be applied to system semiconductors. After vertical stacking, the area occupied by transistors is halved, theoretically doubling the integration density per unit area, meaning twice as many transistors can be placed on a wafer of the same size.

Prior to the paper's publication, the industry's smallest gate pitch for vertically stacked transistors was 48 nanometers. Samsung's research team reduced this to 42 nanometers, achieving a finer process. Power efficiency is directly proportional to the number of transistors per unit area. Since the vertical stacked structure doubles the number of transistors, power efficiency also doubles. Traditional semiconductor processes typically improve performance by about 15% per generation, while the vertical stacked structure, due to the doubling of transistor count, can theoretically achieve a 100% performance improvement. The paper scored 8.29 out of a perfect 10 at the VLSI Symposium, ranking among the top of over 1,000 submitted papers, paving a new path for next-generation logic semiconductors.

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