en.Wedoany.com Reported - Keysight Technologies USA has introduced an Electrical-Optical-Electrical (EOE) simulation solution in ADS 2026 for data center and Ethernet design. Keysight announced the solution on May 21 in Santa Rosa, California, USA. Engineering teams can simulate the complete link from electrical signals to optical signals and back to electrical signals within a single design environment, identifying cross-domain design issues before moving to silicon realization.
The key value of this ADS 2026 update lies in integrating electronic links, photonic devices, and system-level Ethernet verification into a single simulation workflow. AI infrastructure and high-performance computing are driving up the demand for optical interconnect speeds. Optical links between CPUs, GPUs, and high-speed SerDes interfaces require simultaneous consideration of electrical and optical behavior. Traditional workflows often handle electrical simulation and optical simulation separately, requiring engineers to manually stitch results together, which can easily miss the impact of cross-domain interactions on system performance. Keysight states that the EOE capability can simulate the complete signal path from the transmitter, through optical and photonic circuits, to the electrical receiver. Combined with the Keysight High Speed Digital workflow and Keysight Photonic Designer, it enables engineering teams to evaluate electrical-optical design trade-offs and signal integrity under high-speed standards earlier.
Product release information for ADS 2026 Update 2.0 shows that Photonic Designer W3803B has added Electrical-Optical-Electrical end-to-end simulation capabilities and expanded its optical component library, covering modules such as Directly Modulated Laser, Multi-Mode Fiber, Single Mode Fiber, Mach-Zehnder Modulator, Phase Shifter-Modulator, Avalanche Photodiode, Optical S-parameter simulation block, LED, Behavioral Waveguide, and Photo detector.
This solution addresses the increasingly inseparable physical problems in high-speed Ethernet links. Keysight explains that engineers can simultaneously simulate high-speed SerDes digital channels and photonic IC behavior before prototype verification, thereby discovering signal integrity issues that only become apparent when the electronic and optical domains are modeled together. Full-duplex optical link simulation can capture forward and reverse signal propagation in the EOE channel. Wavelength Division Multiplexing support can be used for multi-channel interconnects, helping engineers evaluate nonlinear effects when multiple wavelengths are used simultaneously on the same waveguide for 800G and 1.6T optical links. Noise modeling also covers both the electrical and optical domains, avoiding the fragmented analysis of these two types of noise and link loss. The solution can also capture modulator bias-related nonlinearities and large-signal nonlinearities, and bridges electrical channels with optical envelope simulators through a patented multi-domain co-simulation bridge, reducing the need for engineers to repeatedly switch between different tools.
Beyond system-level EOE simulation, ADS 2026 also covers the design flow from system to component optimization. Through circuit-level PDK support and component-level Keysight RSoft integration, engineering teams can obtain photonic IC representations closer to real chip behavior, reducing the gap between system-level simulation and actual devices. Niels Fache, Senior Vice President at Keysight, stated that AI infrastructure relies on 800 Gbps and 1.6 Tbps optical links for massive data transmission, and at these speeds, electrical and optical performance can no longer be modeled separately.
Keysight Technologies USA's addition of EOE simulation in ADS 2026 reflects that high-speed interconnect design for AI data centers is shifting from single-domain optimization to joint electrical-optical design. For Ethernet chip, optical module, photonic integrated circuit, and high-speed system engineering teams, the ability to identify nonlinearity, noise, dispersion, bit error rate, and eye diagram quality issues before tape-out and hardware prototyping is directly impacting the development cycle and verification risk for 800G, 1.6T, and future higher-speed links.
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