en.Wedoany.com Reported - On May 25, at the IEEE International Symposium on Circuits and Systems (ISCAS) 2026, He Tingbo, Board Director and President of Huawei's Semiconductor Business Unit, delivered a keynote speech titled "Exploration and Practice of a New Path for Semiconductors," formally proposing a new principle for the semiconductor industry's development—the Tao (τ) Law. Huawei defines it as a new guiding principle for the evolution of semiconductors and electronic systems. Its core is replacing "geometric scaling" with "time (τ) scaling," compressing signal propagation delay through technologies like logic folding to increase transistor density and system performance.
This law responds to the dual physical and economic pressures faced by the continued shrinking of advanced process nodes. In the past, semiconductor performance improvement mainly relied on geometric scaling, i.e., continuously reducing transistor size and increasing the number of transistors per unit area. However, as transistor dimensions approach the scale of a few atoms, lithography, interconnects, resistance-capacitance, leakage, power consumption, heat dissipation, and manufacturing costs are all rapidly escalating, weakening the cost benefits brought by traditional Moore's Law. The Tao (τ) Law proposed by Huawei shifts the focus from "how much further can linewidths shrink" to "how fast signals and data travel between devices, circuits, chips, and systems, how low the loss is, and how short the path is." This is the core of what outsiders call "bypassing process node anxiety": advanced process nodes remain important, but performance improvement no longer relies solely on a single manufacturing node. Instead, it continues to compress the time constant through the co-optimization of structure, interconnect, architecture, software, and system.
Logic folding is the most engineering-oriented technical focus within the Tao (τ) Law. Huawei disclosed that this technology breaks through traditional planar layout boundaries, significantly shortening the routing length of critical paths and reducing resistance and capacitance loads during signal propagation, thereby enhancing transistor density and circuit performance.
According to Huawei's multi-level co-optimization framework: at the device level, the device-level time constant is reduced by optimizing transistors, interconnect resistance, and parasitic capacitance; at the circuit level, critical paths are shortened through logic folding; at the chip level, through full-stack co-design of software, architecture, and chips, control instruction flows and data flows are refined around real workloads; at the system level, by defining the Lingqu Bus and reconstructing computing system interconnect protocols, unified memory addressing and native memory semantics for super nodes are achieved, reducing system communication latency. This framework breaks down "chip performance" into multiple optimizable links, including the transistor itself, as well as on-chip interconnects, packaging, buses, memory access, task scheduling, and communication efficiency in large-scale AI clusters.
Huawei also disclosed that over the past six years, based on the Tao (τ) Law, it has successfully designed and mass-produced 381 chips, covering various industry needs. The Kirin chip planned for release in the fall of 2026 will be the first to adopt logic folding technology. It is estimated that by 2031, the transistor density of high-end chips based on the Tao (τ) Law will reach a level equivalent to a 1.4-nanometer process node. A Reuters report also mentioned that Huawei stated at a Shanghai semiconductor conference that its high-end chips would achieve transistor density equivalent to a 1.4nm process by 2031, but independent performance data has not yet been provided. The "equivalent to 1.4nm level" here should be understood as a target for transistor density or system performance, and cannot be directly interpreted as Huawei having mastered a 1.4nm manufacturing process in the traditional sense.
In expert interpretations, He Hui, Head of Semiconductor Research at Omdia, believes that Huawei is proposing a shift from traditional node-driven scaling to system-level efficiency scaling. When advanced lithography is constrained, extracting more performance by shortening interconnects, reducing latency, and improving data movement within the chip is a credible performance extraction path. Counterpoint Research analyst Brady Wang cautioned that cost, power consumption, heat, and system integration remain major challenges, especially more pronounced in cloud AI server scenarios. He Tingbo also acknowledged that this path still faces difficulties such as new chip design tools and overheating control, with challenges spanning from mobile chips to large-scale AI data centers.
The industrial implication of the Tao (τ) Law centers on how Chinese semiconductor companies can find new performance growth paths against the backdrop of constrained advanced process nodes, rapidly rising AI computing power demands, and accelerating competition in post-Moore's Law routes. For smartphone chips, logic folding can focus on critical paths, area density, power consumption, and terminal heat dissipation. For Ascend AI chips and large-scale clusters, system interconnection, memory semantics, inter-chip communication, and data movement efficiency will directly impact training and inference performance. Reuters reported that Huawei plans to use LogicFolding in the Kirin chips to be launched later this year and apply it to Ascend chips and large AI clusters composed of hundreds to thousands of chips around 2030.
Subsequent milestones for the project include whether the new generation Kirin chip in the fall of 2026 adopts logic folding technology as scheduled, the progress of system-level applications in Ascend chips and AI clusters, whether related EDA and design tool chains are adapted to the Tao (τ) Law, and whether the 2031 transistor density target can be verified through products and third-party testing. What can be confirmed at this stage is that Huawei has officially published the Tao (τ) Law at ISCAS 2026, and provided logic folding, multi-level co-optimization, and the 2031 transistor density target. This principle cannot be directly written as meaning that advanced process node restrictions have disappeared, nor can it be expanded to claim that Huawei has already mass-produced 1.4nm process chips.
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