en.Wedoany.com Reported - On July 3, He Tingbo, head of Huawei's semiconductor division, released Version 2 of "Time Scaling Theory for Multi-Level Electronic Systems" (also known in the industry as "Tao's Law") on ChinaXiv, the Chinese Academy of Sciences' preprint platform. Compared to Version 1 released on May 25, the new version adds extensive engineering implementation details, quantitative measured data, and product evolution roadmaps, further refining the post-Moore scaling theory system centered on the time constant τ.

Version 2 integrates the introductory sections of Version 1 into a complete eight-chapter discourse system, with clearer logical layering across chapters. The new version also adds multiple schematic and physical diagrams covering core technologies such as the τ-layered spatiotemporal model, LogicFolding architecture, bonding interface cross-sections, Unified Bus interconnect architecture, and the Hi-ONE optical engine.

In terms of engineering implementation, Version 2 provides an in-depth explanation of the gear ratio concept in the core LogicFolding technology. When the hybrid bonding pitch approaches the dimensions of top-level metal wiring, the 3D design space shifts from traditional "macro-block-level discrete optimization" to "cell-level continuous optimization," enabling globally optimal vertical logic partitioning and breaking through the limitation of conventional 3D stacking, which only allows functional block-level layering.

Version 2 also adds a mass production measured data table, clearly specifying voltage, frequency, normalized power consumption, area, and power density parameters for the Kirin 2026 and the baseline Kirin 9030 Pro.

Furthermore, Version 2 refines the full-scenario roadmap, clarifying technology evolution milestones. On the mobile side, it supplements evolution paths such as moving TSV from the top metal layer down to the M6 layer and stacking multiple active layers; on the AI side, it specifies the iteration cadence of the Ascend series accelerators.