en.Wedoany.com Report on Mar 30th, The research team at the Shenzhen International Quantum Academy recently demonstrated a silicon-based quantum processor capable of performing a complete set of universal logic gate operations. This processor represents the first characterization of universal logical operations in a silicon spin platform, offering a new pathway for the development of quantum computing hardware.
The device is based on five phosphorus donor nuclear spins, which are embedded in an isotopically purified silicon-28 lattice and patterned with atomic precision via scanning tunneling microscope lithography. To combat environmental noise, the system employs a [[4, 2, 2]] quantum error detection code, using four physical qubits to encode two logical qubits. This silicon-based quantum processor architecture has garnered attention due to its compatibility with standard semiconductor manufacturing processes.
On the technical implementation front, the research team characterized a universal logic gate set, including single-qubit Clifford gates, simultaneous Hadamard gates, and two-qubit CNOT gates. The non-Clifford T gate was realized through a gate teleportation method, involving auxiliary nuclear spins to inject phase rotations. Experimental data shows an average physical gate fidelity exceeding 95%, with a logical coherence time of approximately 208 microseconds. The system exhibits significant noise bias, where phase-flip errors dominate over bit-flip errors, potentially reducing the hardware requirements for large-scale fault-tolerant architectures.
To evaluate the processor's practicality, researchers applied the variational quantum eigensolver algorithm to calculate the ground-state energy of a water molecule (H2O). Using three error mitigation techniques—parity check, Clifford data regression, and symmetry verification—the average energy deviation was 22.7 mHa from the theoretical value. This result confirms the feasibility of running practical quantum algorithms on logical silicon qubits. Future work will focus on reducing crosstalk between donor clusters and scaling the architecture to accommodate more complex error correction schemes.
