en.Wedoany.com Reported - Siemens and NVIDIA recently announced a chip verification advancement in the United States. Leveraging Siemens' Veloce proFPGA CS hardware-assisted verification system and NVIDIA's performance-optimized chip architecture, they captured trillions of pre-tapeout design cycles within days, bringing higher efficiency to AI chip verification.

This achievement can help accelerate the development of AI/ML system-on-chip (SoC) designs and gives NVIDIA's team the opportunity to run larger workloads and optimize designs before the first silicon is available. Siemens stated that the Veloce proFPGA CS supports designers and system architects in refining their solutions by running and capturing trillions of verification cycles before the first silicon is ready.

Jean-Marie Brunet, Senior Vice President and General Manager of Hardware-Assisted Verification at Siemens Digital Industries Software, said: "NVIDIA and Siemens collaborate across multiple areas, most recently in advancing hardware-assisted verification methodologies, and specifically FPGA-based prototyping, to meet the verification and validation demands of highly complex AI/ML SoCs. Veloce proFPGA CS helps customers consistently find the best solution for single-FPGA IP verification as well as multi-trillion-gate chiplet designs by combining a highly flexible, scalable hardware architecture with advanced, easy-to-use implementation and debug software flows."

Narendra Konda, Vice President of Hardware Engineering at NVIDIA, said: "As AI and compute architectures grow more complex, semiconductor teams need high-performance verification solutions to validate massive workloads and accelerate time to market. Combining NVIDIA's performance-optimized chip architecture with Siemens' Veloce proFPGA CS enables designers to capture trillions of cycles within days, providing the scale needed to ensure reliability for next-generation AI."

Industry analysis points out that Field-Programmable Gate Array (FPGA)-based prototyping systems offer faster operating speeds, allowing pre-tapeout verification workloads to be completed in a relatively short time. However, as AI/ML design complexity increases, traditional simulation tools face more limitations in terms of cycle scale and efficiency. With the continuous growth in AI chip verification demands, the ability to capture large-scale cycles in less time has become a crucial condition for improving AI chip verification efficiency.

Siemens stated that this advancement helps shorten product development cycles and improve the reliability of complex SoC designs. For semiconductor teams requiring AI chip verification, AI chip verification, AI chip verification, and FPGA-based prototyping are becoming more prominent technical paths. Through continuous optimization of the AI chip verification process, Siemens and NVIDIA aim to provide more scalable support for the development of next-generation AI chips.

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