en.Wedoany.com Reported - Panacea and Meta have each disclosed their validation results for CXL (Compute Express Link) within their respective high-performance data center infrastructures.

At the International Symposium on Computer Architecture (ISCA 2026) held in Raleigh, North Carolina, USA, from June 27 to July 1 local time, Panacea presented performance validation results for its self-developed chip-based CXL controller and port-based routing (PBR) switch. PBR is a method of transmitting data based on device port IDs. Unlike hierarchical routing (HBR) used in existing PCIe and early CXL, which only supports tree-structured connections, PBR can accommodate various network topologies, making it suitable for large-scale memory expansion. Panacea stated that applying next-generation CXL controllers and PBR switches can expand memory scaling to dozens of servers or more while maintaining low memory access latency.

Meta, the U.S. tech company that delivered a keynote speech on CXL that same day, also disclosed similar results. After using CXL chips to expand memory and running actual business services in its data centers, Meta found that the number of servers required for distributed AI inference was reduced by up to 25%, and the average response time for distributed caching was shortened by approximately 29%, achieving cost reduction and performance improvement.

The validation results from both companies underwent approximately six months of review by a panel of industry and academic experts (peer review), and their validity was recognized. Panacea CEO Jeong Myung-soo stated that, combining the two validation results released at this ISCA, CXL is now ready for real-world data center deployment, spanning controllers, design assets (IP), chip implementation, routing, operating system support, to large-scale data center deployment. He also noted that, with expert validation, CXL is expected to begin widespread adoption as memory demand grows in the AI era.