en.Wedoany.com Reported - Intel has filed a patent for a new high-speed memory architecture called Cross-Batch Memory (XBM), aiming to address the cost and packaging challenges of traditional HBM with a different approach. The patent, published on July 2, 2026 (filed on December 26, 2024), was submitted by Underfox and describes XBM as "ultra-high bandwidth memory with back-end transistors." Its core goal is to replace traditional DRAM and its ultra-wide interface with back-end-of-line (BEOL) transistors and Universal Chiplet Interconnect Express (UCIe) serial links, while maintaining a physical size comparable to HBM4.
Understanding the changes proposed by Intel requires knowledge of how standard HBM works. HBM stacks DRAM chips vertically on a logic base die, connected through through-silicon vias (TSVs), and communicates with the processor via a silicon interposer using an extremely wide parallel interface (approximately 1,024 bits per stack). This width provides high bandwidth but also leads to high packaging costs and scalability challenges, as each line must be routed between memory and compute chips through the interposer. As AI accelerators outpace memory supply capabilities, the "memory wall" has become a major performance bottleneck, prompting nearly all major chipmakers to focus innovation on interfaces and stacking.
The first major change in XBM lies in its structure. While traditional DRAM cells are built in the front-end-of-line (FEOL) process, XBM moves the 1T1C cell to the back-end-of-line (BEOL) process, using thin-film transistors to build memory in the metal and via stack above the transistor layer, enabling the chip to be packaged into many independently addressable small memory blocks.
The second change is the interface. Instead of HBM's wide parallel PHY, XBM serializes data into 32 GT/s UCIe bundles, with the base die handling the serialization/deserialization steps. Adopting a standard chiplet interconnect makes this design "chiplet-native," and according to Intel, its packaging is simpler and cheaper than interposer-bound HBM stacks. At 32 GT/s, this is already the highest data rate for current UCIe, and the interface operates at the specification limit.
The patent details a memory-on-package (MoP) structure and "reverse overhang," aimed at reducing stack height (Z-height)—which traditional MoP may increase by 300 to 350 micrometers—while eliminating stiffeners used for warpage control and powering the DRAM directly from the voltage regulator. This forms the basis for the claim of "smaller, cheaper packaging."
XBM should not be confused with ZAM (Z-Angle Memory), an architecture co-developed by Intel and SoftBank subsidiary SAIMEMORY. ZAM's innovation lies in the bonding side—a nine-layer diffusion bonding stack using mostly traditional DRAM with approximately 3-micrometer silicon thickness between layers—reportedly targeting about twice the bandwidth density of HBM4, with commercialization aimed at 2029. XBM, on the other hand, is an independent Intel submission that changes the DRAM transistors themselves and the interface. This indicates Intel is pursuing at least two HBM alternatives in parallel. Currently, the patent was filed 18 months ago with no product or roadmap yet; the UCIe interface is already at its speed limit, and BEOL DRAM has not been verified at manufacturing scale.
For the industry, this patent signals that Intel is seriously seeking alternatives to traditional HBM. If successfully implemented, XBM could significantly reduce AI system costs by eliminating the need for expensive silicon interposers.
