en.Wedoany.com Reported - SK hynix, in collaboration with researchers from TetraMem and the University of Southern California, has developed a memristor-based in-memory computing (IMC) system-on-chip (SoC) designed for AI edge devices. The chip aims to accelerate neural network inference in lightweight AI models, consuming only a fraction of the power of high-end GPUs or NPUs. This SoC primarily serves as a proof-of-concept chip, with a theoretical best peak performance of approximately 2.54 TOPS, which is 16 times lower than the requirements for Microsoft Copilot+.

In-memory computing (IMC) accelerates neural networks by performing analog computations directly within the memory array, thereby reducing data movement and power consumption. However, depthwise convolution (DWC), a core operation in lightweight networks like MobileNet, executes independent per-channel filtering with limited data reuse, making it difficult to efficiently map onto traditional crossbar arrays. To address this limitation, the researchers developed an SoC that integrates both conventional IMC crossbar arrays and a memristor-based IMC architecture specifically optimized for DWC.

The jointly developed SoC is based on an embedded RISC-V processor for workload scheduling and includes 10 neural processing units (NPUs). Among them, one NPU is dedicated to depthwise convolution, while the remaining nine perform pointwise and dense operations. Each of the nine NPUs contains a 256×256 memristor crossbar array for executing analog vector-matrix multiplication (VMM); 256 8-bit DACs to convert digital activation values into analog voltages; 256 8-bit ADCs to convert analog outputs back to digital values; and additional peripheral circuits for reading, writing, programming, and controlling the crossbar array. The NPU optimized for DWC replaces the traditional array with eight specialized 252×28 zigzag crossbar blocks but retains the DACs and ADCs. SK hynix developed and manufactured the memristor devices, integrating the resistive switching cells on top of 65nm CMOS circuits using its back-end-of-line process.

This DWC-optimized NPU is a key feature of the entire SoC. To accelerate depthwise convolution, TetraMem replaced the straight selection lines used in conventional 1T1R crossbar arrays with a zigzag topology. This NPU contains eight 252×28 crossbar blocks, where diagonal selection lines activate 252 memory cells spanning 28 columns, enabling 28 independent 3×3 convolutions to run in parallel while 100% of the array is used for weight storage. The remaining nine NPUs retain traditional 1T1R crossbar arrays for 1×1 pointwise and dense layers, maintaining the throughput and energy efficiency of conventional in-memory computing.

To demonstrate the architecture, the researchers deployed a customized MobileNetV1Small neural network for the Visual Wake Words benchmark. The network contains approximately 36,000 parameters; all depthwise convolution layers are mapped to the dedicated NPU, while pointwise layers are mapped to the remaining NPUs. Since memristor-based IMC hardware natively performs unsigned analog vector-matrix multiplication, inputs and weights are quantized to unsigned 8-bit values before execution. The effective precision of each memristor device can only be programmed to slightly above 2 bits, so the design employs a dual-subarray compensation technique to boost the effective weight precision to approximately 4 bits.

In terms of accuracy, the SoC achieves 80.36% end-to-end inference accuracy, matching the corresponding 4-bit software model. In terms of performance, the SoC delivers a peak throughput of 0.254 TOPS per NPU, with an energy efficiency of 21.3 TOPS/W at 100 MHz and 11.9 TOPS/W at 400 MHz. According to the authors, despite being fabricated using an older 65nm process, this performance surpasses published SRAM-based in-memory computing accelerators. The joint paper claims that the SoC's energy efficiency is an order of magnitude higher than that of the NVIDIA A100 INT8, though these claims remain largely unverified.

Researchers from SK hynix, TetraMem, and the University of Southern California have developed a memristor-based IMC SoC featuring a novel depthwise convolution accelerator that improves crossbar array utilization for lightweight AI workloads. The collaborators successfully fabricated and operated the chip using an outdated 65nm process technology, achieving an energy efficiency of 21.3 TOPS/W and inference accuracy comparable to a 4-bit software model. While the architecture validates the feasibility of the approach, the paper does not disclose the full performance of the SoC, nor is it clear whether all 10 NPUs on the chip can operate at saturation.