en.Wedoany.com Reported - Taiwan Semiconductor Manufacturing Company Limited (TSMC) held its 2026 Taiwan Technology Forum in Hsinchu. Yuan Liben, Senior Director of Advanced Technology Business Development in TSMC's Business Development Organization, officially announced that the world's largest 5.5x reticle size CoWoS has entered mass production, with yields exceeding 98%. Three advanced process nodes unveiled concurrently—A13, A12, and N2U—also made their debut, pushing the competition in the AI chip sector from single-node showdowns toward a generational leap in system-level integration.
At the forum, Yuan Liben systematically elaborated on TSMC's "three-layer cake" platform architecture for AI chips, encompassing three core technology modules: SoIC (chip stacking), CoWoS (heterogeneous integration), and COUPE (optical interconnect). Among these, CoWoS integrates AI GPUs and HBM high-bandwidth memory onto the same large silicon interposer, forming the core carrier of AI computing power. As reticle sizes continue to expand, the number of HBM stacks that can be accommodated rises correspondingly: according to the published roadmap, the 14x reticle size CoWoS to be launched in 2028 will be able to integrate 20 HBM stacks; plans for 2029 aim to further break through the 14x reticle size limit, accommodating up to 24 HBM stacks.
"No matter how powerful a single chip's performance is, if the path to memory isn't wide enough, computing power will be firmly pinned in place." Yuan Liben's comment points directly to the core logic behind the architectural shift—whether it's the computing capability of a GPU or an ASIC, it relies on HBM to provide a continuous stream of data throughput. The CoWoS yield breaking through the 98% mark provides the fundamental guarantee for the mass production of such super-chips that are extremely dependent on high-density interconnects. If yields were low, such complex designs could only remain in the laboratory phase and could not enter commercial deployment.
The scale of capacity expansion also widens the gap with competitors. Yuan Liben disclosed that over 80% of CoWoS capacity is currently used to support AI-related applications, and TSMC will continue to expand CoWoS and SoIC capacity at a compound annual growth rate exceeding 85% in the future. TSMC's CoWoS production capacity is expected to sprint to a monthly output of 90,000 to 110,000 wafers by the end of this year, and further climb to 170,000 wafers by the end of next year.
In the direction of optical interconnect technology, TSMC is advancing the commercial deployment of COUPE. The world's first 200Gbps micro-ring modulator has started production this year, with measured bit error rates below one in one hundred million. As AI servers move from deployment scales of hundreds of thousands of GPUs to millions, traditional copper wire transmission is gradually approaching its physical limits, making optical interconnect the key technological breakthrough for the next generation of AI computing power expansion.
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