en.Wedoany.com Reported - Marvell has launched the Teralynx T100, a 102.4 Tbps Ethernet switching chip platform designed for the AI infrastructure market. The chip begins sampling to customers this quarter, and according to Marvell, it is the first switch at this bandwidth tier optimized specifically for AI and cloud-scale data center networks.
Marvell stated that the Teralynx T100 is manufactured using a 3nm process, with typical power consumption below 1000 watts, targeting energy efficiency—a key constraint for AI cluster operators. With GPU and XPU rack power consumption approaching 120 kW, the chip consumes up to 25% less power than competing products. Since network components account for approximately 15-25% of total rack power consumption, Marvell positions the low-power switching chip as a solution that enables operators to deploy more accelerators within existing facility power limits without expanding power infrastructure.
The Teralynx T100 supports both scale-out and scale-up for AI networks. It can support up to 512 port radix, suitable for large-scale Ethernet AI clusters, while also adapting to emerging scale-up network protocols, including Ethernet Scale-Up Network (ESUN) and Ultra Ethernet Consortium requirements. The device offers multiple packaging options, including standard BGA, co-packaged copper, and co-packaged optics, providing hyperscale data centers with flexibility to adapt to evolving optical interconnect strategies in next-generation AI clusters.
This chip is a 102.4 Tbps Ethernet switching chip optimized for AI and cloud infrastructure; typical power consumption is below 1000W, and according to Marvell, it consumes up to 25% less power than competing products. It utilizes advanced 3nm process technology, supports up to 512 port radix for scale-out AI networks, and supports ESUN, Ultra Ethernet Consortium specifications, and evolving AI Ethernet networks. Packaging options include BGA, co-packaged copper, and co-packaged optics, with SDK, OCP SAI support, and SONiC compatibility. Sampling begins this quarter.
Rishi Chugh, Vice President and General Manager of Marvell's Data Center Switch Business Unit, said: "The Teralynx T100 is purpose-built for AI, designed without legacy power overhead, to deliver the deterministic performance and efficiency required for scaling next-generation data center infrastructure."
Marvell launches the Teralynx T100 as the AI networking chip market enters a new phase defined by power constraints, cluster scale, and architectural specialization. Previous generations of Ethernet switching chips evolved from enterprise and cloud networking requirements, while the T100 reflects a shift toward chips specifically optimized for AI training and inference networks. In these networks, latency, congestion management, and energy efficiency directly impact GPU utilization. The 102.4 Tbps class is becoming a new competitive arena for next-generation AI cluster interconnects. This launch expands Marvell's broader AI infrastructure portfolio, including switching chips, optical DSPs, custom ASICs, co-packaged optics, and interconnect technologies. Competition in the AI networking stack remains intense, with multiple vendors such as Broadcom, NVIDIA, and Cisco driving high-bandwidth, low-power network architectures for clusters scaling to tens or hundreds of thousands of accelerators.
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