en.Wedoany.com Reported - Imec, the global semiconductor research center, has released its latest process technology roadmap, predicting that 3-angstrom (0.3nm) transistors will be manufactured by 2038. The roadmap also indicates that the scaling of contacted poly pitch (CPP) will stop at the A10 generation in 2030, marking a fundamental shift in the chip industry. This roadmap serves as a key reference for industry giants such as TSMC, Intel, Nvidia, AMD, Samsung, and ASML.

According to Imec, the industry is currently in the 2nm (N2) era, with a CPP of approximately 48nm and a cell height of about 132nm. Julien Ryckaert, Vice President of R&D at Imec, stated that the nanosheet era will drive the industry deep into the Angstrom node. Imec predicts that the A14 generation will emerge in 2028, with CPP shrinking to 45nm and cell height dropping to 115nm. TSMC is expected to begin high-volume production using A14 by the end of 2028. Around 2030-2031, A10 or 1nm-class technology is anticipated to debut with a 42nm CPP and 98nm cell height. Imec believes that gate-all-around (GAA) transistors will remain the mainstay. Imec agrees with TSMC that backside power delivery (BSPDN) will not become mandatory for all applications soon, as many applications will not benefit from it. Imec also expects high numerical aperture extreme ultraviolet (High-NA EUV) lithography tools to be used starting from the A14 generation, aligning with Intel's plans.

The Imec roadmap becomes particularly noteworthy at the A7 generation, expected in 2033. At this node, CPP remains at 42nm, but cell height is significantly reduced to approximately 80nm through a 4.5-track architecture. A7 marks the starting point where complementary field-effect transistors (CFET) become a serious candidate for mass production. CFET vertically stacks n-type and p-type transistors, adding a third dimension to transistor scaling. Ryckaert explained that at the A7 generation, traditional nanosheet technology faces increasing scaling challenges, making CFET the solution for the next transistor era.

Beyond A7, the roadmap relies on the evolution of CFET. The A5 generation, expected around 2035-2036, maintains a 42nm CPP but reduces cell height to approximately 64nm. By 2038, the roadmap reaches A3, with a CPP of 39nm and a cell height of 50nm. At this point, Imec envisions sequential CFET implementations and ultimately bonded CFET structures to leverage vertical integration. To achieve a 39nm CPP and 50nm cell height, chip manufacturers may need to use hyper numerical aperture extreme ultraviolet (Hyper-NA EUV) lithography scanners.

The Imec roadmap redefines the meaning of Moore's Law. In the past, Moore's Law referred to transistors becoming smaller, with the number of transistors per unit area doubling every 18-24 months. Imec shows that CPP stagnates at 42nm from A10 to A5, effectively acknowledging that classical transistor scaling has exhausted its momentum. Future density gains must come from vertical integration. Due to different transistor architectures, 3D integration, or backside power delivery, chip designers can integrate more logic gates into a specific area. The industry may shift focus from gate pitch or how many nanometers a single transistor has to standard cell size. The transition from a 6-track cell at N2 to a 3-track cell at A3 illustrates how future density advantages will depend on shrinking standard cell height.

Given all the changes the industry has undergone, Imec believes it is entering a new era called Heterogeneous Large-Scale Integration (HLSI). This concept reflects a shift from traditional very-large-scale integration (VLSI) scaling to a model that integrates multiple technologies into a single computing platform. Future systems will rely on heterogeneous integration of logic, memory, power delivery circuits, and optical I/O, using advanced 3D and 3D+2.5D packaging technologies. Imec expects AI workloads to be the primary driver of semiconductor demand. To optimize future platforms, Imec has established a Cross-Technology Co-Optimization (XTCO) framework, unifying developments in logic, memory, interconnects, power delivery, cooling, and packaging.

As individual chips become denser and more power-hungry, power delivery is expected to become a critical bottleneck. All leading chipmakers—Intel, Samsung, and TSMC—are or will be implementing backside power delivery technology and integrated voltage regulators (IVR) to reduce losses and improve efficiency. Imec expects future AI accelerators and CPUs to rely on a combination of BSPDN, IVR, embedded capacitors, and advanced power semiconductors. More power conversion stages are expected to migrate from racks and motherboards to the package itself. Thermal management issues are becoming increasingly important, with thermal power density expected to increase linearly with transistor count. Ryckaert emphasized that the ultimate goals are to reduce energy consumption for data transmission, increase thermal design power (TDP) to improve thermal management, and enhance computational density. Imec's semiconductor roadmap predicts logic process technology up to the A3 generation around 2038 and argues that Moore's Law can continue despite the slowdown in traditional transistor scaling. According to the roadmap, traditional gate-all-around nanosheet transistors should remain viable until the A10 generation, while CFET architecture will become a mass-production candidate around the A7 generation in 2033. Future transistor density gains are expected to come from vertical integration, reduced standard cell area, and ultimately sequential and bonded CFET structures, rather than aggressive transistor size reduction.