en.Wedoany.com Reported - On July 2, local time, SanDisk announced that samples of its 10th-generation 3D NAND flash memory technology, BiCS10 1Tb TLC, are now available. This product increases the number of storage layers to 332 and integrates Toggle DDR6.0, SCA protocol, and PI-LTT technology, targeting high-speed, low-power, and high-density data storage needs.
The BiCS10 1Tb TLC continues SanDisk's BiCS 3D NAND architecture and adopts CBA wafer bonding technology, where CMOS logic and storage arrays are manufactured separately before being precisely bonded wafer-to-wafer. This approach allows for continued increases in storage density within a limited chip area, while leaving design room for interface speed, power control, and I/O efficiency. According to SanDisk's published data, the storage density of BiCS10 TLC exceeds 29 Gb/mm², a 59% improvement in bit density compared to the 8th-generation 3D flash currently in mass production. The NAND interface speed reaches up to 4.8 Gb/s, a 33% increase. For SSDs, enterprise storage, and high-throughput data devices, higher interface speeds mean improved data transfer capabilities between NAND particles and the controller. Subsequent coordination with controllers, firmware, channel architecture, and packaging solutions is required to translate this into overall drive performance.
The 332-layer stack reflects that 3D NAND continues to advance toward higher layer counts and greater density. As the number of layers increases, the manufacturing process must address challenges such as deep hole etching, thin film deposition, inter-layer consistency, yield control, and reliability verification. The technical difficulty is not merely about stacking higher.
SanDisk also emphasized Toggle DDR6.0, SCA protocol, and PI-LTT technology. Toggle DDR6.0 is used to enhance NAND interface transmission capabilities. The SCA protocol separates the command/address input bus from the data transfer bus, allowing these two types of signals to operate in parallel, thereby reducing data input/output time. PI-LTT reduces power consumption during data input/output by utilizing both the existing 1.2V power supply and an additional low-voltage power supply in the NAND interface power source. Official data states that compared to BiCS8, BiCS10 TLC reduces data input power consumption by 10% and output power consumption by 34%. These improvements will impact the energy efficiency of mobile devices, client SSDs, enterprise SSDs, and data center storage, especially against the backdrop of growing AI datasets, video content, log data, and mixed hot and cold data in the cloud. Storage devices need to balance capacity, throughput, power consumption, and long-term operational stability.
With the BiCS10 1Tb TLC entering the sampling stage, downstream customers will need to continue advancing efforts around controller adaptation, firmware tuning, package design, system validation, and reliability testing. The journey from NAND samples to scaled integration into end products typically involves customer validation, platform certification, production ramp-up, and combinations of different capacity models. This announcement from SanDisk is not about a new end-product SSD, but an update to the underlying flash memory technology node. It will subsequently influence the design space for consumer SSDs, enterprise SSDs, embedded storage, data center storage, and high-capacity flash memory products. As AI-driven workloads expand, data reading, model parameter storage, training sample management, and inference logs will all continue to increase. The improvements in 3D NAND density, interface speed, and energy efficiency will continue to factor into storage system selection criteria.
