en.Wedoany.com Reported - Panmnesia announced that its next-generation Compute Express Link (CXL) controller and Fabric switch technology has been accepted by "ISCA 2026," the top academic conference in the field of computer architecture.
ISCA 2026 will be held from June 27 to July 1 in Raleigh, North Carolina, USA, and is a prestigious academic conference in the field of international computer architecture. Recently, with the widespread adoption of large-scale applications such as AI agents, the demand for memory capacity has grown significantly. At this year's ISCA, two organizations, Meta and Panmnesia, will publish papers related to CXL.
The technology disclosed by Panmnesia this time differs from traditional methods, which connect memory devices directly to the central processing unit (CPU). The new technology uses a CXL switch to connect more devices while achieving both low latency and high bandwidth.
CXL shares a physical interface with PCIe. Therefore, it is common practice to quickly develop a controller by modifying existing design intellectual property (IP), but retaining the original PCIe design operations unchanged can lead to additional latency. The next-generation CXL controller developed by Panmnesia improves upon this, supporting lower latency. The key change involves transforming the process where each layer separately sets up buffers and manages timing independently into a structure where different layers share buffers, significantly reducing synchronization overhead. Additionally, through further optimization of each layer, controller latency has been improved.
In terms of the CXL switch, the new technology supports Port-Based Routing (PBR). Unlike Hierarchical-Based Routing (HBR), which previously only allowed devices to be connected in a hierarchical structure, PBR enables devices to be connected in any form, thereby forming an interwoven Fabric topology. Panmnesia's next-generation CXL switch supports both PBR and HBR, allowing for further optimization of data transmission paths. The company explained that combined with its CXL controller that reduces synchronization overhead, latency can be further reduced.
Panmnesia emphasized that compared to the previous common method of connecting a Multi-Host Device (MHD) directly to the CPU, this technology enables larger-scale memory expansion while maintaining comparable latency and high bandwidth. The paper specifically noted that performance remained stable after connecting 64 servers via the next-generation CXL Fabric switch.
Panmnesia stated that it will further optimize the next-generation CXL switch introduced at ISCA, develop a PCIe 6.4-CXL 3.2 converged switch, and has already obtained a pre-release chip. The next-generation CXL controller, based on continuous technological optimization, has added features of the latest standard CXL 4.0 and has been commercialized as a "PCIe 7.0-CXL 4.0 combined IP."
Panmnesia CEO Jeong Myung-soo (정명수) pointed out that in the past, the industry generally believed that adding a switch between the CPU and devices would make it difficult to meet memory access latency requirements, making direct MHD-to-CPU connection the mainstream approach. He stated that this research proves these characteristics are not inherent limitations of CXL or CXL switches, but rather features of early CXL, and that this issue can be resolved as the standard and related products mature. By using a Fabric switch equipped with a next-generation CXL controller, it is possible to simultaneously achieve high scalability, low latency, and stable processing performance, and confirming this is of great significance.
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