en.Wedoany.com Reported - On July 12, the roadmap for Apple's next-generation M7 series chips was further revealed. Bloomberg reporter Mark Gurman disclosed that Apple plans to launch the base M7 in the first half of 2027, followed by the M7 Pro and M7 Max in the second half of 2027, with the M7 Ultra expected to enter the product lineup in 2028. Among these, the M7 Ultra's chip and memory system are being designed to support up to 1.5TB of unified memory, roughly double the capacity of the planned M5 Ultra's maximum 768GB configuration. Apple has not officially announced these chips, nor has it confirmed that the final product will necessarily offer a 1.5TB option.
Current reports cannot confirm that "Apple has started taping out the M7 six months after the M6 tape-out." What can be confirmed is that the planned release dates for the base M6 and M7 may be only about six months apart; tape-out, sample validation, and official launch are different technical stages and should not be conflated into the same timeline.
Apple may only release the base M6 this time, without continuing development of the M6 Pro, M6 Max, and M6 Ultra, with subsequent high-performance Mac chips directly transitioning to the M7 series. The base M7 is expected to focus on adjustments to the neural engine module and further increase unified memory bandwidth; related reports suggest a target bandwidth of approximately 240GB/s, higher than the M5 base's 153GB/s. Memory bandwidth determines the speed at which the processor, graphics cores, and neural engine read data. In local large model inference, weight data must be continuously transferred from unified memory to compute units; insufficient capacity limits the size of models that can be loaded, while insufficient bandwidth causes compute cores to wait for data.
The 1.5TB of the M7 Ultra is not designed like multiple memory sticks installed on a traditional desktop motherboard. Apple's chips use a unified memory architecture, where the CPU, GPU, neural engine, and media processing modules share the same memory pool, eliminating the need for data to be repeatedly copied between discrete VRAM and system memory. This architecture reduces transfer latency, but the number of memory chips, package area, controller channels, and chip interconnects must be determined simultaneously during the processor design phase, meaning users cannot later expand it like a standard workstation.
When unified memory capacity increases to 1.5TB, chip design faces challenges beyond just adding memory chips. The memory controller must manage more physical addresses and concurrent access channels, while the package must handle longer signal paths, higher total bandwidth, and the power consumption of numerous memory chips operating simultaneously. The M7 Ultra is expected to be used in high-end Macs and Apple's internal artificial intelligence servers, where model parameters, key-value caches, intermediate tensors, and system data can all reside in unified memory when running large models. If the processor uses lower-precision data formats, the 1.5TB capacity can accommodate larger models, but the actual number of runnable parameters still depends on quantization methods, context length, software framework overhead, and memory bandwidth, and cannot be simply converted from memory capacity to fixed model parameters.
Whether Apple will actually sell a 1.5TB version remains uncertain. Reports indicate that the M7 Ultra is only designed to have this maximum addressing and connectivity capability, and the final available capacity will be influenced by memory chip supply, packaging yield, and product configuration adjustments. Apple has already canceled some large memory options for certain M3 Ultra Mac Studio models this year, and current configurations do not fully match the chip's theoretical support limits.
After the M7, Apple is also developing the next-generation M8 architecture, with one processor internally codenamed Soko, expected to launch around 2028; another set of chips for higher-end Macs uses the codename Cardinal. These processors are reportedly set to use TSMC's 1.4-nanometer manufacturing process. This process node is expected to further shrink logic unit dimensions and accommodate more compute modules within the same chip area, but no public information is yet available on the M8's CPU core count, GPU scale, neural engine structure, or memory interface specifications.
From the disclosed development sequence, the M7 series is not a single chip but a system-on-chip architecture covering different compute scales. The base M7 is expected to first enter entry-level Macs, the M7 Pro and M7 Max will handle higher graphics and parallel computing loads, and the M7 Ultra will support workstation and server tasks through larger chip interconnects, unified memory control, and thermal structures. Currently, the 1.5TB unified memory, 240GB/s base memory bandwidth, Soko and Cardinal codenames, and 1.4-nanometer process all come from supply chain or insider disclosures; Apple has not yet released official technical specifications.
