EU Chip Joint Venture Launches €50 Million Quantum Chip Pilot Line
2026-07-14 09:56
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en.Wedoany.com Reported - The EU Chips Joint Undertaking (Chips JU) has launched Q-PLANET (Quantum Chip Stability Pilot Line), a €50 million (approximately $57.2 million) project dedicated to manufacturing industrial-grade components for neutral atom quantum computing, sensing, and communication platforms. Coordinated by hardware developer Pasqal, the project unites 28 research and technology organizations (RTOs), academic groups, and industrial partners across 11 EU member states to build a pan-European manufacturing backbone.

Based on a six-year framework cooperation agreement, the project aims to address the scalability bottleneck of near-term quantum processors by establishing standardized, reproducible semiconductor design and assembly processes. The transition of neutral atom quantum hardware from custom laboratory assembly to mass production is constrained by the lack of standardized manufacturing control loops and system calibration baselines. Q-PLANET's mission is to bridge this operational gap by designing, manufacturing, and verifying chip-based hardware subsystems.

In the first three-year phase, the consortium will optimize three core product categories. For on-chip laser systems, it will manufacture integrated laser sources and amplifiers operating at four key wavelengths: 461 nm, 698 nm, 795 nm, and 1013 nm. These wavelengths are essential for trap manipulation, cooling, and state readout of neutral atom qubits, such as strontium and ytterbium. For advanced atom chips, it will design microfabricated planar chips for atomic confinement to reduce the footprint and power budget of scalable quantum processing units (QPUs). For microfabricated vapor cells, it will develop miniature chip-scale gas cells with internal electrodes and anti-relaxation coatings to support atomic clocks, quantum memories, and Rydberg-based electromagnetic field sensors.

To lower market entry barriers for startups and small and medium-sized enterprises (SMEs), Q-PLANET will formalize these microfabrication processes into open standardized process design kits (PDKs) and assembly design kits (ADKs). These toolkits provide hardware engineers with pre-validated component layouts and automated assembly guidelines, decoupling hardware design from custom cleanroom engineering. The consortium distributes semiconductor foundry, software integration, and packaging responsibilities across specialized centers. For silicon nitride (SiN) foundries, the Technical University of Denmark (DTU) leverages its cleanroom infrastructure as a foundry for passive optical components at 461 nm and 795 nm bands; VTT Technical Research Centre of Finland operates the foundry and test line for 1013 nm SiN devices and leads the chip-to-fiber active pigtailing and packaging work package. For III-V semiconductor factories, TopGaN and the Institute of High Pressure Physics of the Polish Academy of Sciences (Unipress) manage the design, wafer-level characterization, and processing of gallium nitride emitters for the 461 nm blue laser line; III-V Lab provides parallel design and foundry support for 795 nm and 1013 nm architectures. For control middleware and APIs, iQrypto is building a standardized Linux API and a common middleware layer on its software stack, providing users with a unified software interface to interactively manage high-speed electronic modulators and FPGA-driven pulse controllers for quantum components. For metrology and verification, the Istituto Nazionale di Ricerca Metrologica (INRiM) is responsible for noise and linewidth verification tests across all four target wavelengths, utilizing narrow optical filters and metrology clocks to certify physical qubit performance boundaries.

Integrated components will undergo system verification on active test platforms, including Pasqal's commercial neutral atom QPU, the QRydDemo demonstration platform at the University of Stuttgart, and Welinq's quantum memory nodes. By evaluating energy consumption metrics and architectural performance, the project aims to advance target hardware from Technology Readiness Level 4 (TRL 4) to industrially validated TRL 6.

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