en.Wedoany.com Reported - A research team at Yonsei University has developed an ultra-low-power, compact real-time receiver optimized for High Bandwidth Memory (HBM), aimed at improving data transfer speeds and reducing power consumption.

On July 16, the research team led by Professor Park Kwan-seo of Yonsei University announced the achievement. A receiver is a circuit that receives input data signals and accurately distinguishes binary 0s and 1s, capable of detecting and compensating for skew and phase distortion that may occur within memory, helping to ensure reliable data transmission. The technology was demonstrated earlier this year at the 2026 IEEE International Solid-State Circuits Conference (ISSCC) and is expected to contribute to more reliable data transmission in next-generation HBM interfaces.

Skew refers to the difference in arrival times of signals across individual memory data channels. Phase represents the timing relationship between a data signal and the reference clock used to read that signal, while phase drift refers to the gradual shift of this timing relationship over time. These effects are primarily caused by temperature and voltage variations during semiconductor operation and can lead to bit errors. As the number of data channels increases, timing issues become more pronounced. HBM uses more input/output (I/O) channels than traditional memory to achieve higher bandwidth—for example, HBM4 has 2048 I/O pins, whereas standard DDR5 memory has about 32 pins per channel. A large number of I/O channels are used to provide the data bandwidth required for high-performance artificial intelligence (AI) computing.

The research team's real-time receiver supports data transfer speeds of up to 14 gigabits per second (Gbps) per HBM I/O pin. Fabricated using a 28nm process, the receiver consumes only 0.163 picojoules (pJ) per bit of data processed, with a circuit area of just 0.00547 square millimeters. The researchers achieved high precision by combining a time-window-based phase detector (TWPD) with background voltage offset self-calibration technology. TWPD, an ultra-lightweight timing sensor, creates a current path based on minute timing differences between two reference clocks and measures the charge of the input signal; its simple architecture helps reduce power consumption. The background offset calibration technique compares two consecutive sampling results, allowing phase information and offset information to be analyzed independently. Traditional methods struggle to distinguish between the two, as both are embedded in the same sensor output.

Real-time phase tracking has previously been available for wired communication receivers, but its high power consumption and large circuit area have limited its application in HBM. Current HBM receivers typically rely on a training process that aligns timing when the memory or system is first powered on. When phase drift occurs during operation, data transmission must be paused to allow the system to retrain and realign timing, which interrupts high-speed data transfer and reduces effective bandwidth. Professor Park stated that current HBM employs an ultra-high bit-density two-dimensional stacked architecture with 2048 channels, and due to space constraints, it is difficult to integrate dedicated real-time receivers for each channel. A more likely commercial implementation would group approximately 32 channels under one receiver to form a more efficient architecture. He added that achieving this approach will require further chip-level architectural design and commercialization research.