en.Wedoany.com Reported - Qualcomm has officially unveiled its latest near-memory computing architecture, High Bandwidth Computing (HBC), designed to overcome the memory wall bottleneck that has long constrained AI processing performance.
In its announcement, Qualcomm stated that the HBC architecture separates the AI accelerator from the system-on-chip (SoC) and places it directly beneath the LPDDR DRAM stack. The accelerator connects to the LPDDR stack through through-silicon vias (TSVs) to provide high bandwidth and high capacity without the need for expensive HBM memory and advanced packaging. Qualcomm claims the architecture delivers 6x the bandwidth per watt of HBM and over 200x the capacity of on-chip SRAM.
Tony Pialis, Executive Vice President and General Manager of Qualcomm's Data Center Business, explained, "By separating the AI accelerator from the XPU and placing the XPU directly beneath the DRAM stack, we achieve the performance advantages of SRAM along with the density and capacity of stacked memory, thereby eliminating HBM-related bottlenecks." He added that this approach reduces power consumption and heat, removes the costly silicon interposer, and allows enterprises to integrate multiple HBC stacks using standard packaging to improve performance per cost.
Similar explorations have been made in the industry. Fabless ASIC design service company GUC previously proposed DRAM-on-Logic (DoL) technology, stacking up to four layers of DRAM on top of logic to achieve approximately 5 TB/s memory bandwidth. Since Qualcomm has not disclosed specific performance data for HBC, direct comparison with GUC's solution is currently difficult. Additionally, Qualcomm has not specified the exact functions of the HBC accelerator; it could be a dedicated near-memory transformer engine, a collection of tensor cores, or preprocessing logic for AI inference or training.
Qualcomm also revealed the HBC roadmap. The AI200 accelerator, set to launch later this year, will use LPDDR5X and provide 43 TB of RAM per rack. The subsequent product, AI250, will feature first-generation HBC with 18x the bandwidth of the AI200. The AI300 will adopt second-generation HBC, offering 54x the bandwidth of the AI200.
Qualcomm has recently strengthened its position in the AI market through several strategic initiatives, including completing a $4 billion acquisition and launching the Snapdragon C product for entry-level laptops, priced at approximately 4 million Indonesian rupiah. The introduction of the HBC architecture comes amid intense competition in the semiconductor industry, with rumors about Samsung's Exynos 2600 drawing attention to the latest process node developments. Qualcomm emphasizes that its focus extends beyond processors to more efficient memory solutions.
Compared to HBM technology, Qualcomm's solution uses standard packaging and cheaper LPDDR memory to deliver a solution at lower cost. However, questions remain about the effectiveness of HBC across various AI workloads. Without detailed specifications and performance benchmarks, it is difficult to objectively evaluate Qualcomm's claims.
Meanwhile, memory innovation continues in the semiconductor industry. NEO Semiconductor recently announced that its 3D X-DRAM for AI processors has passed proof of concept. Samsung has demonstrated the first HBM5 prototype using Heat Path Block cooling technology. For Qualcomm, the success of HBC will depend on market adoption, as it must convince server and data center manufacturers of the architecture's added value.
Qualcomm plans to drive multi-generational development of HBC technology. The AI250 with first-generation HBC promises an 18x bandwidth improvement, while the AI300 with second-generation HBC will offer a 54x improvement. If realized, these numbers would represent a massive performance leap in the AI field.
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