en.Wedoany.com Reported - On July 10, Shanghai Lingrui Zhixin Computing Technology Co., Ltd. announced the next phase of its processor development plan, advancing the tape-out of the high-performance RISC-V CPU core P100, chip verification, and agent CPU product development, while continuing to refine the AI-native converged computing architecture. The R&D scope covers CPU cores, chiplets, domain-specific processors, and system software adaptation, with target applications including artificial intelligence data centers, cloud computing, edge computing, embodied intelligence, and autonomous driving.
The P100 is a high-performance RISC-V CPU core developed by Lingrui Zhixin for servers and high-concurrency computing tasks. The core adopts an ultra-deep, ultra-wide out-of-order superscalar pipeline, capable of scheduling multiple instructions simultaneously and adjusting execution order based on instruction dependencies, reducing processor idle cycles caused by waiting for data. The P100 also supports dynamic simultaneous multithreading technology, allowing a single CPU core to run up to four hardware threads and switch between different thread modes based on workload. When multiple threads run concurrently, the processor can dispatch instructions from different tasks to idle execution units, improving the utilization of internal computing resources within the core.
The currently disclosed P100 performance metric is a SPECint2006 single-core score exceeding 20/GHz. This value measures integer computing performance and is normalized by operating frequency, but the final chip's operating frequency, core count, cache capacity, and manufacturing process for the P100 have not yet been disclosed.
The P100 is also equipped with server-grade reliability, availability, and serviceability (RAS) design, including error detection, error isolation, and core recovery. When local computing errors, cache anomalies, or partial execution unit failures occur within the processor, the RAS mechanism must identify the fault location, prevent erroneous data from propagating to other modules, and maintain the operation of other cores and threads as much as possible. Data center processors typically need to operate continuously for extended periods, and a brief failure in a single computing node can impact ongoing model inference, databases, and cloud services. Therefore, in addition to computing performance, the core must be configured with machine check, error reporting, and recovery control links. Lingrui Zhixin has previously run the Linux operating system on FPGA prototype platforms and hardware emulation platforms, and current R&D efforts will shift from core functional verification to physical chip implementation.
Before tape-out, the R&D team must complete logic design, functional verification, timing closure, power analysis, physical layout, and manufacturability checks. The P100 supports out-of-order execution and four-thread concurrency, requiring the core's instruction scheduler, register renaming unit, execution ports, and cache system to handle more in-flight instructions simultaneously, thereby increasing verification complexity. After the design enters wafer manufacturing, the team must also perform startup testing, instruction set consistency testing, operating system adaptation, performance testing, and long-term stability verification on sample chips to confirm that functions verified in FPGA and emulation environments operate correctly on actual silicon.
Processor products based on the P100 are not limited to delivering a single CPU core. Lingrui Zhixin will also develop chiplets and domain-specific processors around the core, combining general-purpose computing cores with AI acceleration, data movement, interface control, and security modules. The chiplet approach allows different functional modules to be designed and manufactured separately, then packaged together in the same processor system via high-speed interconnects. Customers can also embed the P100 core into different types of system-on-chips through IP licensing, joint development, or custom development. This technical roadmap requires simultaneous development of compilers, firmware, Linux kernel support, drivers, and performance tuning tools to prevent the chip from being unable to enter actual business systems due to insufficient software adaptation after completion.
The AI-native converged computing architecture is another part of this R&D phase. In addition to running large models, agent systems must frequently perform task decomposition, tool invocation, data reading, process control, and multi-program concurrency, generating continuous interactions between the CPU, AI accelerators, memory, and input/output devices. Lingrui Zhixin plans to handle the coordination between general-purpose computing and AI tasks at the microarchitecture level, enabling the CPU not only to manage the system but also to participate in agent task scheduling, data preprocessing, and control-intensive computations.
Funding for this R&D phase comes from hundreds of millions of yuan in new financing completed by Lingrui Zhixin, with participants including China's Zhangjiang Hi-Tech, China's Zhongke Chuangxing, China's Oriental Fortune Capital, China's Chengwei Capital, China's Shixi Capital, and China's Biren Technology. The funds will primarily be used for P100 tape-out verification, agent CPU development, converged computing architecture R&D, and expansion of the technical team. The specific financing amount and investment proportions from each party have not been disclosed.
Currently, the P100 has completed verification on FPGA and emulation platforms, and the next step is to enter tape-out and post-silicon testing. The number of processor cores based on the P100, chip packaging scheme, initial tape-out timeline, wafer manufacturing process, and mass production milestones have not yet been disclosed.
