en.Wedoany.com Reported - On July 13, Shanghai Eastern Computing Core Technology Co., Ltd. officially released the DF1000 series of high-performance AI chips. This product adopts a "software-defined chip + 3D near-memory computing" architecture, targeting computing scenarios such as large model training, distributed inference, and single-machine inference. Under BF16 precision, the peak computing power reaches 520 TFLOPS, memory access bandwidth reaches 6.4 TB/s, and Scale-up interconnect bandwidth reaches 900 GB/s. Eastern Computing Core calls the DF1000 "the world's first large-computing-power software-defined near-memory computing 3D chip," a statement primarily derived from the company and conference preparation reports. The product is scheduled to debut at the 2026 World Artificial Intelligence Conference, held from July 17 to 20.
The DF1000 does not solely rely on more advanced chip manufacturing processes to increase transistor density but instead attempts to enhance actual usable computing power through computing architecture, software scheduling, and three-dimensional packaging. Its software-defined chip technology splits different types of computing tasks for spatial parallel processing and uses time-division multiplexing of hardware resources, allowing the same set of computing units to undertake different tasks at different stages. Eastern Computing Core believes this approach can reduce the long-term idling of some hardware resources, improving computing resource utilization under domestic mature process conditions. The company's official website summarizes this technology as a full-stack reconfigurable computing system, organizing AI tasks using a coarse-fine-grained fused dataflow programming method.
The performance bottleneck of artificial intelligence chips does not solely stem from the number of computing units. When running large models, weights, caches, and intermediate computation results must be continuously read from video memory. If the processor's computing speed exceeds the data transfer speed, computing units may idle while waiting for data—a phenomenon often referred to as the "memory wall." The DF1000 employs 3D hybrid bonding technology to vertically integrate the computing layer and memory layer, shortening the data transmission distance between computing units and memory through wafer-level stacking. Eastern Computing Core disclosed that its interconnect pitch has been reduced from tens of micrometers in traditional packaging to sub-micrometer levels, improving interconnect density and bandwidth density. The publicly displayed internal chip model adopts a three-layer structure, with the computing layer in the middle and memory layers on the top and bottom.
The 6.4 TB/s memory access bandwidth primarily serves data exchange between the chip's internal computing and memory, while the 900 GB/s Scale-up interconnect bandwidth is used for high-speed communication between multiple chips. The former determines whether a single chip can obtain model data in a timely manner, and the latter relates to data synchronization capabilities during multi-card server and supernode expansion. Both metrics collectively influence the actual operational efficiency of large model training and inference clusters.
The DF1000 utilizes a domestic supply chain for chip design, wafer manufacturing, and packaging testing, and complies with the OAM 2.0 form factor specification, allowing it to be integrated into AI server platforms with corresponding standard interfaces. Eastern Computing Core has established a product system extending from chips to servers, supernodes, and computing clusters. In addition to the DF1000 AI accelerator card, this system includes the 64-card Tuoyu TY64 supernode using standard Ethernet interconnection, the high-density liquid-cooled Qingyuan QY100 server, and the Huisuan HS512 cluster. According to the company's official website, this product system primarily targets computing scenarios such as large model training and inference, scientific computing, healthcare, energy, transportation, and manufacturing.
From product launch to actual deployment in computing centers, the DF1000 still requires server adaptation, software stack refinement, model migration, cluster interconnection, and long-term load validation. Chip parameters define the theoretical performance ceiling, but data centers are more concerned with effective computing power, stability, power consumption, parallel efficiency, and compatibility with different model frameworks during large model operation. Eastern Computing Core has stated that it will prioritize applications for enterprises, universities, and research institutions in Shanghai, gradually expanding its usage scope. The company will also showcase servers and computing clusters at the 2026 World Artificial Intelligence Conference. Whether the DF1000 can extend from single-chip parameters to multi-card and large-scale cluster performance will become a key focus of subsequent product validation.
