en.Wedoany.com Reported - On July 18, Shenzhen IntelliFusion Technology Co., Ltd. (688343.SH) unveiled its AI inference chip roadmap for the next two-plus years at the 2026 World Artificial Intelligence Conference (WAIC 2026). The company disclosed three dedicated chips and their cluster-level collaboration solutions, explicitly proposing to advance AI inference from "single-chip competition" to "inference factory competition."
As large models transition from training to large-scale inference deployment, traditional "training-inference integrated" general-purpose chip architectures face bottlenecks in efficiency and cost. Large model inference is primarily divided into the Prefill phase, which processes input context, and the Decode phase, which generates tokens one by one and demands extremely high compute and memory bandwidth—each with vastly different hardware resource requirements.
Based on this insight, IntelliFusion's solution "decouples" the inference chain. Among them, the DeepVerse100P is designed for million-level context Prefill scenarios, aiming to resolve resource contention issues caused by shared resources between Prefill and Decode in traditional hybrid architectures. The DeepVerse100D targets the Decode phase, with memory bandwidth several times that of mainstream chips, supporting a 1024-card Scale-up and optical interconnect system architecture to reduce multi-node communication bottlenecks and tail latency. The DeepVerse100L is designed for the compute-intensive FFN (Feed-Forward Network) segment of the Decode phase, adopting a 3D Memory architecture to significantly increase memory bandwidth and improve parallel efficiency of computation and communication.
Alongside the hardware launch, IntelliFusion proposed a more forward-looking system concept. The company plans to drive the separated deployment and collaborative operation of these three chips in an exascale heterogeneous cluster—configuring corresponding chips and resource pools according to the different load characteristics of Prefill, Decode, and Decode FFN, forming a collaboratively operating heterogeneous computing system through high-speed interconnects. Chen Ning, Chairman and CEO of IntelliFusion, stated that as AI moves toward large-scale application, measuring computing power value should focus more on how many tokens the system can stably and efficiently produce. This solution extends chip optimization from single-chip performance improvement to cluster-level efficiency optimization, aiming to reduce the cost per token generated and move closer to the long-term vision of "one cent for ten billion tokens."
The increased hardware heterogeneity and cluster scale impose higher demands on the software stack. IntelliFusion is continuously building the IFWA software stack, covering AI model development, programming, and system levels, while strengthening adaptation and optimization for PyTorch ATen operators and mainstream inference frameworks such as vLLM and SGLang. Additionally, in May this year, the company, together with multiple organizations in chips, software, models, and applications, launched the "1001 Plan," aiming to feed application requirements back into chip and system design earlier, accelerating technology validation and deployment.
